Stress liners are commonly used to enhance the performance of field-effect transistors (FETs). These stress liners may be used to provide either compressive or tensile stress on the transistor channel. For instance, a silicon nitride (SiN) compressive stress liner is often formed over a P type FET (PFET), and a tensile stress liner is often formed over an N type FET (NFET) such as shown in FIG. 1. Here, a gate 102 (e.g., polysilicon or another conductive material) is disposed over a silicon layer 101. Silicon layer 101 may be a simple silicon layer substrate or it may be part of a larger substrate structure such as a silicon-on-insulator (SOI) structure. Source/drain regions 105 are embedded in silicon layer 101, and sidewall spacers 103 are dispose on opposing sides of gate 102. A tensile SiN stress liner 104 is disposed over silicon layer 101, as well as completely over sidewall spacers 103 and gate 102.
As indicated by the arrows in FIG. 1, the tension provided by tensile stress liner 104 is distributed so as to provide sub-optimal tension where greater tension would otherwise be more effective. Thus, tensile stress liner 104 somewhat works against itself in providing tensile stress to the channel of the illustrated transistor. This is even more so where gate 102 is relatively short.